Silicon that pairs a CAN FD interface with on-chip security.

Secure CAN FD Microcontrollers

Cryptographic protection of CAN traffic starts with the silicon. The controls cataloged on this site assume a device that can both speak CAN FD and hold a key where firmware cannot read it back. This page lists microcontroller families that meet both conditions, so a designer scoping a secured CAN node can see which parts carry the hardware to support it. A family appears only when it has at least one CAN FD interface and at least one hardware security feature.

Microcontroller Families with CAN FD and Hardware Security

The table below is sorted by core architecture, weakest performance first, then by top clock speed within each architecture. Read it as an orientation aid, not a recommendation: it records what each family offers on paper, compiled from public product pages and datasheets. Once a part is in view, the MCU Crypto Benchmarks page measures what the cryptographic primitives actually cost in flash, stack, and time on parts like these.

Microcontroller families combining at least one CAN FD interface with at least one hardware security feature, sorted by core architecture (weakest first) then top clock speed. Compiled from public datasheets; neutral orientation aid, not an endorsement. Last reviewed 30 July 2026.
Mfr Family Architecture Max MHz CAN FD Security features
TRNG Key store Accelerators
Microchip PIC32CM JH Cortex-M0+ 48 2 SHA-256
Microchip dsPIC33C MPT dsPIC33 DSC (16-bit) 100 2 AES-256, ECC, SHA-2/3
NXP MCX E24 Cortex-M4F 112 3 AES-128 (CSEc)
Microchip SAM E5x Cortex-M4F 120 2 AES-256, RSA/ECC (PUKCC), SHA
Infineon PSoC 6 Cortex-M4F 150 1 AES, 3DES, RSA, ECC, SHA
ST STM32G4 Cortex-M4 170 3 AES-256 (crypto line)
Nuvoton M467 Cortex-M4F 200 4 AES-256, RSA, ECC, SHA-2, HMAC
Renesas RX26T RXv3 120 1 AES-256, SHA (TSIP-Lite)
Espressif ESP32-C5 RISC-V (RV32) 240 2 AES, RSA, ECC, SHA-2, HMAC
Renesas RA4C1 Cortex-M33 80 1 AES, ECC, SHA (RSIP)
ST STM32L5 Cortex-M33 110 1 AES-256, RSA/ECC (PKA), SHA
ST STM32C5 Cortex-M33 144 2 AES, SAES, PKA (RSA/ECC), SHA
NXP LPC55Sxx Cortex-M33 (dual) 150 2 AES, RSA, ECC (CASPER), SHA
NXP MCX N94x Cortex-M33 (dual) 150 2 AES-256, ECC, SHA-2 (EdgeLock)
ST STM32U5 Cortex-M33 160 1 AES, RSA/ECC (PKA), SHA
Infineon PSoC Control C3 Cortex-M33 180 2 AES-128, RSA, ECC, SHA-256
GigaDevice GD32E5xx Cortex-M33 180 3 AES, 3DES, RSA/ECC, SHA
GigaDevice GD32F5xx Cortex-M33 200 2 AES, 3DES, RSA/ECC, SHA
Renesas RA6 Cortex-M33 200 2 AES, RSA, ECC, SHA, GHASH
GigaDevice GD32G5xx Cortex-M33 216 3 AES, 3DES, SHA
NXP MCX A26 Cortex-M33 240 2 AES-256 (SGI), RSA/ECC (PKC)
ST STM32H5 Cortex-M33 250 2 AES, SAES, RSA/ECC (PKA), SHA
Nordic nRF54H20 Cortex-M33 (multi-core) 320 1 AES, ChaCha20, ECC, Ed25519, SHA-2/3
TI C2000 F28P65x C28x DSP (dual) 200 2 AES
NXP S32K3 Cortex-M7 240 8 AES, RSA, ECC, SHA-2 (HSE)
Microchip SAM E7x/V7x Cortex-M7 300 2 AES-256, SHA
Microchip PIC32CZ CA Cortex-M7 300 6 AES, 3DES, ChaCha20, RSA, ECC, SHA (HSM)
Infineon XMC7000 Cortex-M7 (dual) 350 2 AES, RSA, ECC, SHA
ST STM32H7 Cortex-M7 550 3 AES-256, 3DES, SHA (crypto line)
GigaDevice GD32H7xx Cortex-M7 600 3 AES, 3DES, SHA
ST STM32H7R/S Cortex-M7 600 2 AES, ECC (PKA), SHA (S line)
NXP i.MX RT1170 Cortex-M7 + M4 1000 3 AES, 3DES, RSA-4096, ECC, SHA (PUF)
Infineon AURIX TC3xx TriCore (multi-core) 300 3 AES-128, ECC, SHA-2 (HSM)
Infineon AURIX TC4x TriCore (multi-core) 500 5 AES, ECC, SHA (HSM + CSRM)
Nuvoton M55M1 Cortex-M55 220 2 AES-256, RSA-4096, ECC-571, SHA-512
ST STM32N6 Cortex-M55 800 3 AES ×2 (DPA-hard), ECC (PKA), SHA
Renesas RA8 Cortex-M85 480 2 AES, RSA, ECC, SHA-2/3, Ed25519 (RSIP)
TI AM263x Cortex-R5F 400 4 AES, 3DES, RSA/ECC (PKA), SHA-2 (HSM)
TI AM243x Cortex-R5F (+M4F) 800 2 AES, 3DES, RSA/ECC (PKA), SHA-2 (SA2UL)
Renesas RZ/T2M Cortex-R52 (dual) 800 2 AES, RSA, ECC, SHA (RSIP)

Frequently Asked Questions

Why does this table list only CAN FD parts?

Cryptographic frame protection needs room for an authentication tag and a freshness counter, and the classical CAN payload of eight bytes leaves almost none. CAN FD carries up to 64 bytes per frame, which is what makes authenticated and encrypted CAN traffic practical. A controller that pairs a CAN FD interface with on-chip security is therefore the natural target for the controls cataloged on this site, so the table is scoped to that combination. A part qualifies only when it has at least one CAN FD interface and at least one hardware security feature.

What counts as secure key storage?

Any on-chip mechanism that holds key material so that firmware and an attacker with debug access cannot read it back. In practice this ranges from a simple write-only or one-time-programmable key region, through immutable secure-boot root keys, to a physically unclonable function or a separate security subsystem such as an HSM or secure enclave that performs cryptographic operations without ever exposing the key. The table marks the feature as present when the datasheet documents such a mechanism; the note names which kind.

Does listing a part imply a recommendation?

No. The table is a neutral orientation aid compiled from public product pages and datasheets. It records what the silicon offers, not a judgment of fitness for any particular design, and inclusion is not an endorsement. EmSA has no commercial relationship with the manufacturers listed. Confirm every specification against the current datasheet before making a selection, because vendors revise part lineups and feature sets over time.